This project deals with the designing of a 32-bit floating-point Multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating-point operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating-point standard representation before any sorts of operations are conducted on them. The floating-point representation for a standard single precision number is a 32-bit number that is segmented to represent the floating-point number.
The IEEE format consists of four fields, the sign of the exponent, the next seven bits are that of the exponent magnitude, and the remaining 24 bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating-point arithmetic processor design includes, Arithmetic Logic Unit (ALU), Register organization, Control & Decoding Unit, Memory block, 32 bit Floating point Multiplication. This processor IP core can be embedded many places such as co processor for Embedded DSP and Embedded RISC controller.
The over all System Architecture will be designed using HDL language and simulation, synthesis and implementation (Translation, Mapping, Placing and Routing) will be done using various FPGA based EDA Tools. Finally the proposed system architecture performance (speed, area, power and throughput) will be compared with already exiting system implementations.
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